White Paper 2 Part II: Die-to-Die Interfaces - A Case for Lowering Component-level CDM ESD Specifications and Requirements (v1.1 November 2023)

Revision 1.1

Adopted as JEDEC JEP196 November 2023

Abstract

This white paper on die-to-die (D2D) interfaces is an extension of the second revision of White Paper 2 on CDM target levels released in 2021. It addresses the need for a clear CDM target roadmap for D2D interfaces.

D2D interfaces are the central intellectual property (IP) blocks for a heterogeneous integration architecture. This heterogeneous integration technology, with several variants of 2.5D and 3D package integration schemes, is the key enabler for the continuation of Moore’s law and will drive the growth of the semiconductor market in the coming years.

This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces. The survey results emphasize the need for a common roadmap.

The three main aspects of the paper are the assessment of the status of electrostatic discharge (ESD) control of the process steps with ESD exposure for D2D interfaces, the stress test approach, and the roadmap of the target values. These recommendations outline the tasks for the industry to get prepared for the use of high-density D2D interfaces in the years to come. The white paper affects IP design, chiplet design, foundry, and the outsourced semiconductor assembly and test (OSAT) industry as well as EDA vendors.

Last Updated on November 29, 2023

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