White Paper 4 - Understanding Electrical Overstress - EOS

Revision 1.2

Updated: 8/25/2016

Abstract  

White Paper 4 Understanding Electrical Overstress - EOS is the first Industry Council white paper dealing with Electrical Overstress (EOS).

Damage signatures from Electrical Overstress are the leading reported cause of returns in
integrated circuits and systems that have failed during operation. Solutions to this problem are
hindered by a prevailing misconception in the electronics industry that insufficient robustness to
electrostatic discharge (ESD) is a primary cause of EOS. This document, White Paper 4, (WP) has
been carefully compiled by the Industry Council on ESD Target Levels to foster a unified global
understanding of what constitutes EOS and how EOS damage signatures can result from a wide
variety of root causes.

The paper begins by outlining a brief history of EOS. It then presents the results of an industry-wide
EOS survey. This survey gathered information on the types of EOS problems experienced by over
80 different companies, the relative importance of EOS to their overall business, and the methods
assigned by these companies to address EOS issues. The survey provides a combined picture from
which a more comprehensive definition of EOS can be made. The numerous categories and sub-
categories of EOS root causes are explored in an attempt to understand how to create better
specifications which will reduce their occurrence. In addition to the survey results, this paper studies
many field returns with EOS damage signatures to establish the underlying root causes of damage
and offers the respective identified solutions.

The survey and the case studies both show that successful failure analysis (FA) depends on careful
communication between customer and supplier from the time a failure occurs until its cause has
been discovered. Detailed investigation into manufacturing and handling processes is often
necessary to accurately identify the root cause. This paper outlines a basic summery of the typical
process flow for component electrical failure analysis.

The key point is that EOS issues can be mitigated when the proper understanding of IC design,
factory and field environments, and system implementation is combined with effective
communication across all these areas.

 

 (Click Here for full Revision 1.2 PDF of White Paper 4) - 5.0MB 

 

 

 

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