White Paper 3 System Level ESD Part II: Implementation of Effective ESD Robust Designs

Revision 2.0 (JEDEC JEP162)


White Paper 3 Part II is the second of two Electrostatic Discharge (ESD) Industry Council white papers dealing with System Level ESD.

In Part I, the misconceptions common in the understanding of system level ESD between supplier and original equipment manufacturer (OEM) were identified, and a novel ESD component / system co-design approach called system efficient ESD design (SEED) was described. The SEED approach is a comprehensive ESD design strategy for system interfaces to prevent hard (permanent) failures. In Part II we expand this comprehensive analysis of system ESD understanding to categorize all known system ESD failure types, and describe new detection techniques, models, and improvements in design for system robustness. Part II also expands this SEED co-design approach to include additional hard / soft failure cases internal to the system.

Part II begins with an overview of system ESD stress application methods and introduces new system diagnosis methods to detect weak ESD failure areas leading to hard or soft failures, and provides a “cost vs. performance vs. robustness” analysis of present-day state-of-the-art EMC/EMI design prevention methods that have been developed to prevent system level ESD failure. It follows with an expansion of SEED failure classifications to cover a combination of hard (permanent) and/or soft (resettable) system failures and stresses which could cause these errors, and describes cases where the SEED co-design approach can be expanded to provide additional benefits to system ESD design. System design simulation tools are described in the context of their potential improvements to simulating system level ESD stress and failure modes. Application-specific industry system ESD test methods are then described in the context of their ability to reveal hard and soft failure modes from actual system deployment. Finally, a technology roadmap of the system design components is described, including IC technology and related circuit speeds, automotive electronics, packaging technology, system / board interconnect technology and ESD protection materials, illustrating continuing challenges for system ESD design improvement.

 (Click Here for full PDF of PART II


 (Click Here for full PDF of previous PART I)