Revision 3.00

Preface
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD level requirements. We will show through this document why realistic lowering of the ESD target levels for component level ESD is not only essential but is also urgent. The document is organized in different chapters to give as many technical details as possible to support the purpose given in the abstract. We begin the paper with an Executive Summary and chapter highlights followed by Frequently Asked Questions (FAQ) so that the reader can readily find critical information without having to scan through the whole document. Additionally, these FAQ are intended to avoid any misconceptions that commonly occur while interpreting the data and the conclusions herein. All component level ESD testing specified within this document adheres to the methods defined in the appropriate JEDEC and ESDA/ANSI specifications. 

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